Mrunal Shende
Logic synthesis, EDA algorithms, and solver-guided optimization for hardware-efficient design.
About
Research
Papers
Projects
Internship
Research Interests
Experience & Education
PhD Candidate
IIT Indore · Dept. of Computer Science & Engineering
- Developing solver-guided techniques for MIG and mMIG optimization, targeting area and depth reduction in logic networks.
- Designed benchmarking pipelines for FPGA/ASIC synthesis flows enabling reproducible comparison of optimization strategies.
- Investigated secure logic synthesis methods using majority-based graph transformations against structural attacks.
- Built automation frameworks across EPFL, ISCAS, and MCNC benchmark suites.
M.Tech — CSE (Cyber Security)
NIT Kurukshetra · Haryana
- Researched shilling attack detection in collaborative filtering recommender systems, combining supervised ML with behavioural profiling.
- Published two conference papers (ICFCS 2023, ITM Web 2023) and one article on recommender system security and cyber-physical systems.
- Explored cyber security techniques at the intersection of machine learning and intelligent transportation systems (ITS).
EDA Intern
Synopsys India Pvt. Ltd.
- Contributed to production-grade logic synthesis tools used in commercial ASIC design flows.
- Worked on optimization passes improving timing closure and area for standard cell–based designs.
- Gained hands-on experience with industrial EDA infrastructure and synthesis tool scalability.
B.E. — Computer Science & Engineering
DY Patil Institute of Technology · Mumbai University
- Undergraduate studies in Computer Science covering algorithms, data structures, operating systems, and computer networks.
mMIG for AQFP-Oriented Logic Optimization
The first publicly available optimization tool for mMIG (minority-Majority Inverter Graphs) — no prior toolchain existed for this graph class. Accepts .v, .blif, and .aig netlists, runs all advanced resubstitution and graph-transformation rules, and returns a provably optimised AQFP circuit.
Secure MIG Logic Synthesis — ISVLSI Extension Study
Benchmark suite and Vivado FPGA evaluation pipeline comparing AOIG, MIG, and mMIG for security-focused logic synthesis. Automates synthesis, implementation, and report generation across all three circuit variants for reproducible ISVLSI results.
Folded-Bias Decomposition for Majority Logic Networks
Introduces folded-bias CSA as a construction method for odd-input majority functions. Provides two circuit approaches with automated Verilog/BLIF netlist generation and one-click reproduction via pre-committed CSV artifacts.
CP-SAT Driven Circuit Optimization Pipeline
End-to-end pipeline for constraint-programming–guided logic optimization. Enumerates K-cuts from BLIF netlists, formulates a CP-SAT ILP for optimal cut selection, then rebuilds the circuit. DAC'19 evaluation flow compatible.
Enhancing popSAD: A New Approach to Shilling Attack Detection in Collaborative Recommenders
ICFCS 2023
Analysing Supervised Learning Approaches for Detecting Shilling Attacks in Collaborative Recommendations
ITM Web of Conferences 54
Incorporation of Cyber Security in Intelligent Transportation Systems (ITS)
Insights2Techinfo
3 journal / transaction manuscripts currently under review. Titles withheld pending publication.
Technical Toolbox
Languages
EDA / CAD Tools
Domains
Systems / Workflow
Get in Touch
Open to research collaborations, discussions, and opportunities.