Mrunal Shende
I work on majority/minority-based logic representations, solver-guided optimization, and reproducible EDA flows for hardware-efficient digital design.
About
Research
Papers
Projects
Internship
Logic Graph Representations
MIG · mMIG · AQFP-oriented cost proxies · technology mapping
Solver-Guided Optimization
CP-SAT · SAT/SMT · design-space exploration · formal equivalence
Reproducible EDA Flows
Benchmark pipelines · CEC-verified outputs · open artifacts
Research Interests
Experience & Education
PhD Candidate
IIT Indore · Dept. of Computer Science & Engineering
- Developing solver-guided techniques for MIG and mMIG optimization, targeting area and depth reduction in logic networks.
- Designed benchmarking pipelines for FPGA/ASIC synthesis flows enabling reproducible comparison of optimization strategies.
- Investigated secure logic synthesis methods using majority-based graph transformations against structural attacks.
- Built automation frameworks across EPFL, ISCAS, and MCNC benchmark suites.
M.Tech — CSE (Cyber Security)
NIT Kurukshetra · Haryana
- Researched shilling attack detection in collaborative filtering recommender systems, combining supervised ML with behavioural profiling.
- Published two conference papers (ICFCS 2023, ITM Web 2023) and one article on recommender system security and cyber-physical systems.
- Explored cyber security techniques at the intersection of machine learning and intelligent transportation systems (ITS).
EDA Intern
Synopsys India Pvt. Ltd.
- Contributed to production-grade logic synthesis tools used in commercial ASIC design flows.
- Worked on optimization passes improving timing closure and area for standard cell–based designs.
- Gained hands-on experience with industrial EDA infrastructure and synthesis tool scalability.
B.E. — Computer Science & Engineering
DY Patil Institute of Technology · Mumbai University
- Undergraduate studies in Computer Science covering algorithms, data structures, operating systems, and computer networks.
Selected Projects
Research artifacts, scripts, generated netlists, and reproduction flows are available through the linked GitHub repositories.
mMIG for AQFP-Oriented Logic Optimization
An open-source prototype for minority-Majority Inverter Graph (mMIG) optimization targeting inverter-aware AQFP-oriented cost proxies. The flow applies minority seeding, dual-inversion propagation, cone polarity flipping, and CEC-guarded design-space exploration, retaining only formally equivalent outputs. The reported AQFP metric is a pre-mapping proxy based on gate and complemented-edge counts.
Secure MIG Logic Synthesis — ISVLSI Extension Study
Benchmark evaluation suite for comparing AOIG, MIG, and mMIG synthesis results across standard benchmarks using Vivado. Packages scripts, Verilog netlists, and generated FPGA reports to enable one-click reproduction of the ISVLSI 2025 results presented in the accompanying paper.
Folded-Bias Decomposition for Majority Logic Networks
Explores folded-bias carry-save adder (CSA) decomposition as a construction technique for threshold circuits realizing odd-input majority functions. Compares a baseline and a folded approach using automated Verilog/BLIF netlist generation; includes pre-committed CSV artifacts for one-click result reproduction.
CP-SAT Driven Circuit Optimization Pipeline
End-to-end pipeline for constraint-programming–guided logic optimization. Enumerates K-cuts from BLIF netlists, formulates a CP-SAT optimization model for cut selection, then rebuilds the circuit. DAC'19 evaluation flow compatible.
Enhancing popSAD: A New Approach to Shilling Attack Detection in Collaborative Recommenders
ICFCS 2023
Analysing Supervised Learning Approaches for Detecting Shilling Attacks in Collaborative Recommendations
ITM Web of Conferences 54
Incorporation of Cyber Security in Intelligent Transportation Systems (ITS)
Insights2Techinfo
Additional manuscripts under review at IEEE venues. Details available upon request.
Technical Toolbox
Languages
EDA / CAD Tools
Domains
Systems / Workflow
Get in Touch
Open to research collaborations, discussions, and opportunities.